Design and Analysis of Two Low Power Source Coupled Logic Structures

This paper presents a novel approach to design robust source coupled logic for implementing ultra low power circuits. In this paper, we proposed two different source coupled logic structures and analyzed the performance of these structures with STSCL. The first design we used DTPMOS as load device and analyses the performance of DTSCL Logic with previous source coupled logic for ultra low power operation. DTSCL circuits exhibit a better power–delay Performance compared with the STSCL Logic. It can be seen that the proposed circuit provides 56% reduction in power delay product. The second design uses basic current mirror active load device to provide required voltage swing. Current mirror source coupled logic can be used for high speed operation. The advantage of this design is that it provides 54%reduction in power delay product over conventional STSCL. The main drawback of this design is that it provides a higher power dissipation compared to other source coupled logic structures. The proposed circuit provides lower sensitivity to temperature and power supply variation, with a superior control on power dissipation [1]. Measurements of test structures simulated in 0.18 μm CMOS technology shows that the proposed DTSCL logic concept can be utilized successfully for bias currents as low as 1 pA [2]. Measurements show that existing standard cell libraries offer a good solution for ultra low power SCL circuits.